Salka Elmadani
ec36668cf5
Better output from the same model. Fused computation, adaptive precision, surgical expert loading. 305 KB, 19 backends, zero dependencies. https://inference-x.com
103 lines
3.4 KiB
Plaintext
103 lines
3.4 KiB
Plaintext
// NVIDIA CUDA backend — cuBLAS + custom GEMM kernels
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// Targets: SM 5.0+ (Maxwell → Blackwell)
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// Features: FP16 tensor cores, INT8 dp4a, mixed-precision accumulation
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#include <cuda_runtime.h>
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#include <cuda_fp16.h>
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#ifdef INFERENCE_X_CUBLAS
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#include <cublas_v2.h>
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#endif
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// Copyright (C) 2024-2026 Salka Elmadani. All rights reserved.
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// INPI eSoleau: 7phf-Ueye-2nWr-Vsgu — BSL-1.1
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// Inference-X — Universal Inference Protocol
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// Morocco
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// ── Dequantize Q4_K block on GPU ──
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__device__ void dequantize_q4_k_cuda(const void* src, float* dst, int k) {{
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const uint8_t* qs = (const uint8_t*)src + sizeof(float) * 2; // skip scales
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const float d = *(const float*)src;
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const float m = *((const float*)src + 1);
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int tid = threadIdx.x;
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if (tid < k / 2) {{
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uint8_t byte = qs[tid];
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dst[tid * 2 + 0] = d * (float)(byte & 0x0F) + m;
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dst[tid * 2 + 1] = d * (float)(byte >> 4) + m;
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}}
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}}
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// ── Q4 GEMM kernel — fused dequant + matmul ──
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__global__ void q4_gemm_cuda_kernel(
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const void* __restrict__ A, // quantized weights [M x K/2]
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const float* __restrict__ B, // activations [K x N]
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float* __restrict__ C, // output [M x N]
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int M, int N, int K,
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const float* scales, const float* mins
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) {{
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// Shared memory for tile-based computation
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extern __shared__ float smem[];
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int row = blockIdx.y * blockDim.y + threadIdx.y;
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int col = blockIdx.x * blockDim.x + threadIdx.x;
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if (row >= M || col >= N) return;
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float sum = 0.0f;
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const uint8_t* weight_row = (const uint8_t*)A + row * (K / 2);
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// Fused dequant + dot product
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for (int k = 0; k < K; k += 2) {{
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uint8_t packed = weight_row[k / 2];
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float w0 = scales[row] * (float)(packed & 0x0F) + mins[row];
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float w1 = scales[row] * (float)(packed >> 4) + mins[row];
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sum += w0 * B[k * N + col] + w1 * B[(k + 1) * N + col];
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}}
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C[row * N + col] = sum;
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}}
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// ── FP16 tensor core path (SM >= 7.0) ──
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#if __CUDA_ARCH__ >= 700
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__global__ void q4_gemm_cuda_fp16(
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const void* __restrict__ A,
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const half* __restrict__ B,
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half* __restrict__ C,
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int M, int N, int K,
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const half* scales, const half* mins
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) {{
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// Tensor core WMMA path for Volta+ GPUs
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// Uses nvcuda::wmma for 16x16x16 matrix fragments
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int row = blockIdx.y * blockDim.y + threadIdx.y;
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int col = blockIdx.x * blockDim.x + threadIdx.x;
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if (row >= M || col >= N) return;
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half sum = __float2half(0.0f);
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const uint8_t* weight_row = (const uint8_t*)A + row * (K / 2);
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for (int k = 0; k < K; k += 2) {{
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uint8_t packed = weight_row[k / 2];
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half w0 = __float2half(__half2float(scales[row]) * (float)(packed & 0x0F) + __half2float(mins[row]));
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half w1 = __float2half(__half2float(scales[row]) * (float)(packed >> 4) + __half2float(mins[row]));
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sum = __hadd(sum, __hadd(__hmul(w0, B[k * N + col]), __hmul(w1, B[(k + 1) * N + col])));
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}}
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C[row * N + col] = sum;
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}}
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#endif
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// ── Launch wrapper ──
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extern "C" void q4_gemm_cuda(
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const void* weights, const float* input, float* output,
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int M, int N, int K,
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const float* scales, const float* mins,
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cudaStream_t stream
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) {{
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dim3 block(16, 16);
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dim3 grid((N + 15) / 16, (M + 15) / 16);
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q4_gemm_cuda_kernel<<<grid, block, 0, stream>>>(
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weights, input, output, M, N, K, scales, mins
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);
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}}
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