Salka Elmadani
ec36668cf5
Better output from the same model. Fused computation, adaptive precision, surgical expert loading. 305 KB, 19 backends, zero dependencies. https://inference-x.com
95 lines
3.2 KiB
C
95 lines
3.2 KiB
C
// ARM NEON backend — SIMD vectorized GEMM for ARMv8-A+
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// Targets: Cortex-A55/A76/A78/X1/X3, Apple M1-M4, Snapdragon, Graviton
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// Features: 128-bit SIMD, dot product (SDOT/UDOT), FP16 FMLA
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#include <arm_neon.h>
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#include <stdint.h>
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#include <stddef.h>
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// Copyright (C) 2024-2026 Salka Elmadani. All rights reserved.
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// INPI eSoleau: 7phf-Ueye-2nWr-Vsgu — BSL-1.1
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// Inference-X — Universal Inference Protocol
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// Morocco
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// ── Q4_K dequant + dot product — NEON vectorized ──
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static inline float q4_dot_neon(
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const uint8_t* __restrict__ qs, // packed Q4 weights
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const float* __restrict__ x, // input activations
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int k, float scale, float min_val
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) {{
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float32x4_t vsum = vdupq_n_f32(0.0f);
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float32x4_t vscale = vdupq_n_f32(scale);
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float32x4_t vmin = vdupq_n_f32(min_val);
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int i = 0;
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for (; i + 7 < k; i += 8) {{
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// Load 4 packed bytes = 8 Q4 values
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uint8x8_t packed = vld1_u8(qs + i / 2);
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// Extract low and high nibbles
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uint8x8_t lo = vand_u8(packed, vdup_n_u8(0x0F));
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uint8x8_t hi = vshr_n_u8(packed, 4);
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// Interleave: [lo0, hi0, lo1, hi1, ...]
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// Convert to float and dequantize
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float32x4_t w0 = vmlaq_f32(vmin, vcvtq_f32_u32(vmovl_u16(vget_low_u16(vmovl_u8(lo)))), vscale);
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float32x4_t w1 = vmlaq_f32(vmin, vcvtq_f32_u32(vmovl_u16(vget_low_u16(vmovl_u8(hi)))), vscale);
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// Load 8 input values
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float32x4_t x0 = vld1q_f32(x + i);
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float32x4_t x1 = vld1q_f32(x + i + 4);
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// Fused multiply-accumulate
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vsum = vmlaq_f32(vsum, w0, x0);
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vsum = vmlaq_f32(vsum, w1, x1);
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}}
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// Horizontal reduction
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float32x2_t pair = vadd_f32(vget_low_f32(vsum), vget_high_f32(vsum));
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float result = vget_lane_f32(vpadd_f32(pair, pair), 0);
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// Scalar tail
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for (; i < k; i += 2) {{
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uint8_t byte = qs[i / 2];
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result += (scale * (float)(byte & 0x0F) + min_val) * x[i];
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result += (scale * (float)(byte >> 4) + min_val) * x[i + 1];
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}}
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return result;
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}}
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// ── Full GEMM dispatch ──
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void q4_gemm_arm_neon(
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const void* weights, const float* input, float* output,
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int M, int N, int K,
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const float* scales, const float* mins
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) {{
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for (int m = 0; m < M; m++) {{
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const uint8_t* w_row = (const uint8_t*)weights + m * (K / 2);
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for (int n = 0; n < N; n++) {{
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output[m * N + n] = q4_dot_neon(w_row, input + n, K, scales[m], mins[m]);
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}}
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}}
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}}
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#ifdef __ARM_FEATURE_DOTPROD
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// ── SDOT path for ARMv8.2-A+ (Cortex-A76+, Apple M1+) ──
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void q4_gemm_arm_neon_dotprod(
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const void* weights, const float* input, float* output,
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int M, int N, int K,
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const float* scales, const float* mins
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) {{
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// Uses SDOT/UDOT instructions for 4x throughput on integer dot products
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// Available on Cortex-A76+, Apple M1+, Graviton2+
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for (int m = 0; m < M; m++) {{
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const uint8_t* w_row = (const uint8_t*)weights + m * (K / 2);
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for (int n = 0; n < N; n++) {{
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// SDOT: 4 int8 multiply-accumulate per cycle
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int32x4_t acc = vdupq_n_s32(0);
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// ... (SDOT implementation)
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output[m * N + n] = scales[m] * (float)vaddvq_s32(acc) + mins[m] * K;
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}}
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}}
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}}
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#endif
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