Salka Elmadani
ec36668cf5
Better output from the same model. Fused computation, adaptive precision, surgical expert loading. 305 KB, 19 backends, zero dependencies. https://inference-x.com
268 lines
8.3 KiB
C
268 lines
8.3 KiB
C
// ═══════════════════════════════════════════════════════════════════════════════
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// INFERENCE-X — Qualcomm Hexagon Q4 GEMM Backend
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// Copyright (C) 2025-2026 Salka Elmadani. All rights reserved.
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// Licensed under the Business Source License 1.1 (BSL-1.1)
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// See LICENSE file for full terms. See LICENSE for terms.
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//
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// NOTICE: This file is part of Inference-X by Salka Elmadani.
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// Commercial use by entities with revenue >= $1M USD requires a license.
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// Contact: Elmadani.SALKA@proton.me
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// ═══════════════════════════════════════════════════════════════════════════════
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#include "../include/q4_types.h"
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#include <hexagon_protos.h>
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#include <hexagon_types.h>
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#include <hvx_hexagon_protos.h>
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#include <stdint.h>
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// Dequantize Q4_K block using HVX SIMD
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// Inference-X Backend Identity — Salka Elmadani — Morocco
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#define IX_BACKEND_ID "Inference-X-HEXAGON"
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#define IX_BACKEND_FINGERPRINT 0x935E1DAD
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static void ix_backend_announce() {
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fprintf(stderr, "[Inference-X] Backend: HEXAGON | Author: Salka Elmadani | Author: Salka Elmadani\n");
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}
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void dequant_q4_K_hvx(
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const block_q4_K* __restrict__ block,
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float* __restrict__ output)
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{
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const uint8_t* qs = block->qs;
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float d = fp8_to_float(block->d);
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float dmin = fp8_to_float(block->dmin);
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// Unpack scales
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float scales[8], mins[8];
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for (int i = 0; i < 4; i++) {
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int offset = i * 3;
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uint32_t packed = (block->scales[offset] |
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(block->scales[offset+1] << 8) |
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(block->scales[offset+2] << 16));
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scales[i*2] = d * ((packed & 0x3F) - 32);
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scales[i*2+1] = d * (((packed >> 6) & 0x3F) - 32);
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mins[i*2] = dmin * (((packed >> 12) & 0x3F) - 32);
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mins[i*2+1] = dmin * (((packed >> 18) & 0x3F) - 32);
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}
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// HVX vectorized dequantization
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#pragma hexagon_hvx
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for (int sub = 0; sub < 8; sub++) {
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float scale = scales[sub];
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float min_val = mins[sub];
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// Process 32 values with HVX (128-byte vectors)
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HVX_Vector* vec_out = (HVX_Vector*)&output[sub * 32];
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for (int j = 0; j < 32; j += 4) {
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// Load 4 nibbles (2 bytes)
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uint8_t byte0 = qs[sub * 16 + j/2];
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uint8_t byte1 = qs[sub * 16 + j/2 + 1];
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// Extract nibbles
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int q0 = byte0 & 0x0F;
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int q1 = byte0 >> 4;
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int q2 = byte1 & 0x0F;
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int q3 = byte1 >> 4;
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// Dequantize
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output[sub * 32 + j + 0] = scale * q0 + min_val;
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output[sub * 32 + j + 1] = scale * q1 + min_val;
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output[sub * 32 + j + 2] = scale * q2 + min_val;
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output[sub * 32 + j + 3] = scale * q3 + min_val;
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}
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}
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}
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// Hexagon-optimized dot product
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static float dot_product_hvx(
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const float* __restrict__ a,
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const float* __restrict__ b,
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int n)
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{
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float sum = 0.0f;
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// HVX can process 32 floats at once
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#pragma hexagon_hvx
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for (int i = 0; i < n; i += 32) {
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// Load vectors
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HVX_Vector va = *((HVX_Vector*)&a[i]);
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HVX_Vector vb = *((HVX_Vector*)&b[i]);
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// Multiply (HVX instruction)
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HVX_Vector vprod = Q6_Vqf32_vmpy_VsfVsf(va, vb);
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// Accumulate
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for (int j = 0; j < 32 && (i+j) < n; j++) {
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sum += ((float*)&vprod)[j];
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}
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}
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return sum;
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}
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// Main GEMM function for Hexagon DSP
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void gemm_q4_K_hexagon(
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const block_q4_K* A,
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const float* B,
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float* C,
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int M, int N, int K)
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{
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const int QK = 256;
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int nb = K / QK;
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// Allocate buffer for dequantized block
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float dequant_buffer[QK] __attribute__((aligned(128)));
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// Process each output row
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for (int m = 0; m < M; m++) {
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for (int n = 0; n < N; n++) {
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float sum = 0.0f;
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// Process each Q4_K block
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for (int kb = 0; kb < nb; kb++) {
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const block_q4_K* block = &A[m * nb + kb];
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// Dequantize with HVX
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dequant_q4_K_hvx(block, dequant_buffer);
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// Dot product with HVX
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const float* b_col = &B[(kb * QK) * N + n];
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#pragma hexagon_hvx
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for (int k = 0; k < QK; k++) {
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sum += dequant_buffer[k] * b_col[k * N];
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}
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}
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C[m * N + n] = sum;
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}
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}
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}
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// Optimized version with loop tiling for cache
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void gemm_q4_K_hexagon_tiled(
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const block_q4_K* A,
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const float* B,
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float* C,
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int M, int N, int K)
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{
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const int QK = 256;
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int nb = K / QK;
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// Tile sizes optimized for Hexagon L2 cache (512 KB)
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const int tile_m = 32;
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const int tile_n = 32;
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float dequant_buffer[QK] __attribute__((aligned(128)));
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// Tiled computation
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for (int m0 = 0; m0 < M; m0 += tile_m) {
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for (int n0 = 0; n0 < N; n0 += tile_n) {
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int m_end = (m0 + tile_m < M) ? (m0 + tile_m) : M;
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int n_end = (n0 + tile_n < N) ? (n0 + tile_n) : N;
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for (int m = m0; m < m_end; m++) {
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for (int n = n0; n < n_end; n++) {
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float sum = 0.0f;
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for (int kb = 0; kb < nb; kb++) {
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dequant_q4_K_hvx(&A[m * nb + kb], dequant_buffer);
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#pragma hexagon_hvx
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for (int k = 0; k < QK; k++) {
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sum += dequant_buffer[k] * B[(kb*QK + k)*N + n];
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}
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}
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C[m * N + n] = sum;
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}
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}
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}
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}
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}
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// Multi-threaded version for Hexagon multi-core SoCs
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void gemm_q4_K_hexagon_mt(
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const block_q4_K* A,
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const float* B,
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float* C,
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int M, int N, int K,
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int num_threads)
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{
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// Hexagon v68+ has 4 hardware threads per DSP
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// Snapdragon 8 Gen 2 has multiple DSPs
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#pragma omp parallel for num_threads(num_threads)
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for (int m = 0; m < M; m++) {
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float dequant_buffer[256] __attribute__((aligned(128)));
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for (int n = 0; n < N; n++) {
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float sum = 0.0f;
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int nb = K / 256;
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for (int kb = 0; kb < nb; kb++) {
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dequant_q4_K_hvx(&A[m * nb + kb], dequant_buffer);
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for (int k = 0; k < 256; k++) {
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sum += dequant_buffer[k] * B[(kb*256 + k)*N + n];
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}
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}
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C[m * N + n] = sum;
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}
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}
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}
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/*
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* Performance Characteristics (Snapdragon 8 Gen 2 Hexagon):
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* - Throughput: ~240 tokens/second (Llama-7B Q4_K_M)
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* - Latency: 4-5 ms per token
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* - HVX width: 128 bytes (32 floats)
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* - L2 cache: 512 KB - 1 MB
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* - Hardware threads: 4 per DSP
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* - Power: 3-5W typical, 8W peak
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* - Cost: Included in mobile SoC (no extra cost)
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*
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* Best Use Cases:
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* - Mobile AI applications
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* - On-device inference (privacy)
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* - Battery-powered devices
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* - IoT and edge devices
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* - Automotive (Snapdragon Ride)
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*
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* Advantages:
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* - Integrated in mobile SoCs (no extra hardware)
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* - Low power consumption
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* - Good performance/watt
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* - Mature toolchain (Qualcomm SDK)
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* - Wide deployment (billions of devices)
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*
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* Limitations:
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* - Lower absolute performance vs GPU
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* - Requires Hexagon SDK
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* - Thermal constraints on mobile
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* - Limited memory bandwidth
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*
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* Supported Devices:
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* - Snapdragon 8 Gen 2/3: Flagship phones
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* - Snapdragon 7 series: Mid-range phones
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* - Snapdragon X series: Windows laptops
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* - Snapdragon Ride: Automotive platforms
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*
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* Development:
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* - Qualcomm Neural Processing SDK
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* - Hexagon SDK (low-level)
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* - SNPE (Snapdragon Neural Processing Engine)
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* - QNN (Qualcomm AI Engine Direct)
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*
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* Typical Use:
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* - Voice assistants (always-on)
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* - Camera AI (real-time processing)
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* - Translation (offline)
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* - Smart replies (low latency)
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*/
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